DRAM arrays are memories comprised of memory cells, wordlines and bitlines, the latter lying orthogonal to the wordlines, the memory cells being located adjacent crossovers of the wordlines and bitlines. Each of the memory cells is typically comprised of an n channel capacitor in series with the source-drain circuit of an n channel access field effect transistor (FET), the gate of which is connected to and is enabled by an associated wordline. This form of cell is referred to as a 2T cell.
A bit of a particular logic level, sensed in a bit line sense amplifier, is stored in each cell. Prior to reading from or writing to a cell, both the bit line and word line are precharged. The bit line is typically precharged to a voltage Vdd/2, and the word line is precharged to Vss, to completely isolate the memory cell capacitor from the bitline.
Because many DRAM production processes are not optimized, cell leakage often occurs, and data retention may not be adequate for some applications. To achieve superior data retention, data can be stored differentially in two individual cells. Each bit is stored as a `0` in one cell and as a `1` in another cell. Leakage will degrade a `1` level in an n-channel cell array, but not a `0`. While common mode disturbances do not affect stored data in this case, thus improving data retention, this reduces the capacity of the DRAM by half.
Some DRAMs also suffer from poor logic "1" voltage levels using the unboosted wordline active voltage Vdd. In this case, a logic "1" voltage level stored would be limited to Vdd-Vtn, where Vtn is the conduction threshold voltage of the cell access FET. In order to achieve better data retention in the DRAM cell the gate of the cell access FET can be driven to Vpp=Vdd+Vtn.
However, there is a significant question of whether a submicron manufacturing process can produce DRAMS which can withstand continuous voltage stress of Vpp, especially under worst case operating conditions.